Research

• Programming approach for heterogeneous multi-cores. We are exploring a programming approach which can tackle the diversity of accelerators, make programs portable across heterogeneous multi-cores and require only an intuitive effort from the programmer.
• Energy efficient and defect-tolerant reconfigurable accelerator tile. After exploring multi-purpose accelerators, we are now investigating an energy efficient reconfigurable tile. We then want to explore how to make this reconfigurable tile defect-tolerant, pushing the limits of defect-tolerance of traditional computing approaches.
• Defect-Tolerant accelerators based on neural networks. Neural networks are an intrinsically defect tolerant computing approach. While hyped in the 1980s and 1990s, hardware neural networks fell out of favor. However, lately, a remarkable convergence of trends in machine-learning, technology and applications are making hardware neural networks particularly attractive again as defect-tolerant accelerators. This effort ranges from artificial neural networks (ANNs) with classic digital CMOS technology, to ANNs for digital signal processing using analog neurons, and up to biologically inspired neural networks, possibly using silicon devices other than transistors. You can find more details in the slides (BibTeX) of the keynote at ISCA 2010. Beyond hardware design, this effort can also lead to the efficient modeling and a better understanding of biological neural networks themselves.

Teaching