Prof. Jean-Luc Gaudiot
	  Electrical and Computer Engineering
	  University of California, Irvine
	  gaudiot@uci.edu

          Lundi 14 Février 2002, 14h00
	  INRIA Rocquencourt, Bâtiment 11 

Memory Latency: to Tolerate or to Reduce?

Abstract :
It has become a truism that the gap between processor speed and memory access latency is continuing to increase at a rapid rate and that this has become the major issue facing high-performance computer designers. This talk presents some of the architecture strategies which are used to bridge this gap. They are mostly of two kinds: memory latency reducing schemes and memory tolerating approaches.

Our HiDISC (Hierarchical Decoupled Instruction Set Computer) is the case study of a successful design which allows the efficient use of caches in applications which exhibit low temporal locality and promises to deliver low latency for general-purpose computing. In contrast, our research in multithreading has shown that long memory latencies could also be masked behind the execution of other threads.

This is proving to be a useful approach whether the memory latency is due to physical location (as in Networks of Workstations) or to the technology of the various memory layers. Indeed, this is the case in single processor, SMT (Simultaneous Multithreading) machines or in distributed systems in which we have implemented our ISSC (I-Structure Software Caches).

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